Re: 68k exception handling

I believe the example you cite both assembles and disassembles correctly.

> 1142F6 1 #Q 0 D1 +X A0) ADD 52B01000 <==== should be
52B01400

Let's take a closer look.

1st word of opcode:
        Bits[15:12] 0101
        Bits[11:9] 001 data ( 1 #Q )
        Bit[8] 0
        Bits[7:6] 10 size (long)
        Bits[5:3] 110 mode (d8,An,Xn)
        Bits[2:0] 000 reg (A0)

2nd word (brief extension format) of opcode:
        Bit[15] 0 D/A (index is a data register)
        Bits[14:12] 001 Reg (D1)
        Bit[11] 0 W/L (index is sign-extended word)
        Bits[10:9] 00 Scale (00=scale *1)
        Bit[8] 0
        Bits[7:0] 0..0 Displacement (0)

Your proposal is for the second word to be 1400 which means the scale field
of the opcode extension word would be 10 which specifies a scale of *4.

--Leon

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Received on Wed Oct 15 2003 - 20:26:48 PDT