Re: Interrupts don't interrupt?!

Hi, OK, I'm a little bit confused now...

One of the main advantages of forth (which I am a newbie to) is the
"interactive development". Now I receive an impression that this doesn't
hold when developing applications with extensive use of interrupts...
Hopefully I'm wrong with that?!
Also, Leon says, the BDM is non-intrusive. But why does it fail when
going into blocking loops for more than about 100.000 iterations? It
should service it's interrupts and returning into my loop, shouldn't it?
To make a clear question of this: Do you recommend forth for developing
hard real-time systems?

And, one last point:

The datasheet of the MCF5485 says that "unique and non-overlapping level
and priority definitions must be assigned to the interrupt control
registers (irc), otherwise undefined behavior may be the consequence.
Applying the word

: ShowICRs
    CR
    ICR-EPF1 C@ . ." IRC-EPF1" CR
    ICR-EPF2 C@ . ." ICR-EPF2" CR
    ICR-EPF3 C@ . ." ICR-EPF3" CR
    ICR-EPF4 C@ . ." ICR-EPF4" CR
    ICR-EPF5 C@ . ." ICR-EPF5" CR
    ICR-EPF6 C@ . ." ICR-EPF6" CR
    ICR-EPF7 C@ . ." ICR-EPF7" CR
   
    ICR-EP0ISR C@ . ." ICR-EP0ISR" CR
    ICR-EP1ISR C@ . ." ICR-EP1ISR" CR
    ICR-EP2ISR C@ . ." ICR-EP2ISR" CR
    ICR-EP3ISR C@ . ." ICR-EP3ISR" CR
    ICR-EP4ISR C@ . ." ICR-EP4ISR" CR
    ICR-EP5ISR C@ . ." ICR-EP5ISR" CR
    ICR-EP6ISR C@ . ." ICR-EP6ISR" CR CR
    ICR-USBISR C@ . ." ICR-USBISR" CR
    ICR-USBAISR C@ . ." ICR-USBAISR" CR
    ICR-USB C@ . ." ICR-USB" CR CR
    ICR-OFUF C@ . ." ICR-OFUF" CR
    ICR-RFOF C@ . ." ICR-RFOF" CR
    ICR-RFDF C@ . ." ICR-RFDF" CR
    ICR-TFUF C@ . ." ICR-TFUF" CR
    ICR-TCF C@ . ." ICR-TCF" CR
    ICR-TFFF C@ . ." ICR-TFFF" CR
    ICR-EOQF C@ . ." ICR-EOQF" CR
    ICR-PSC3 C@ . ." ICR-PSC3" CR
    ICR-PSC2 C@ . ." ICR-PSC2" CR
    ICR-PSC1 C@ . ." ICR-PSC1" CR
    ICR-PSC0 C@ . ." ICR-PSC0" CR
    ICR-TC C@ . ." ICR-TC" CR
    ICR-SEC C@ . ." ICR-SEC" CR
    ICR-FEC1 C@ . ." ICR-FEC1" CR
    ICR-FEC0 C@ . ." ICR-FEC0" CR
    ICR-I2C C@ . ." ICR-I2C" CR
    ICR-PCIARB C@ . ." ICR-PCIARB" CR
    ICR-CBPCI C@ . ." ICR-CBPCI" CR
    ICR-XLBPC C@ . ." ICR-XLBPC" CR
   
    ICR-XLBARB C@ . ." ICR-XLBARB" CR
    ICR-DMA C@ . ." ICR-DMA" CR
    ICR-CAN0 C@ . ." ICR-CAN0" CR
    ICR-BUSOFF0 C@ . ." ICR-BUSOFF0" CR
    ICR-MBOR0 C@ . ." ICR-MBOR0" CR
   
    ICR-SLT1 C@ . ." ICR-SLT1" CR
    ICR-SLT0 C@ . ." ICR-SLT0" CR
    ICR-CAN1 C@ . ." ICR-CAN1" CR
    ICR-BUSOFF1 C@ . ." ICR-BUSOFF1" CR
    ICR-MBOR C@ . ." ICR-MBOR" CR
   
    ICR-GPT3 C@ . ." ICR-GPT3" CR
    ICR-GPT2 C@ . ." ICR-GPT2" CR
    ICR-GPT1 C@ . ." ICR-GPT1" CR
    ICR-GPT0 C@ . ." ICR-GPT0" CR
;

to an fresh project says that

ICR-EPF1 = 8 and ICR-SLT0 = 8

ICR-EPF4 = 32 and ICR-PSC0 = 32

The priority levels of the EPFs are hardcoded in the processor - may it
be an error in the forth system to assign the same prios to the SLT0 and
PSC0 or is this intentional for any reason?

Cheers,

Gerry

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Received on Sun Apr 22 2007 - 04:11:58 PDT